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matrixofdynamism
Xilinx MPSoC and RFSoC, what is the big deal?
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on: July 25, , 11:10:26 am »
Xilinx invented the Zynq device which combined an ARM core with programmable logic. This was more than 15 years ago I believe.
More recently they released MPSoC and RFSoC FPGAs. From what I know these are massive FPGAs and contained multi-core ARM processors. Now the question in my mind is, what is the big deal? What makes these MPSoC and RFSoC devices special or distinct? We have had ARM core with programmable logic for more than a decade in the market and from different suppliers as well.
Herby
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #1 on: July 25, , 11:23:52 am »
As far as I can tell, you've answered your own question already. They're more modern versions of the Zynq. They're bigger, faster and more expensive, but there's nothing fundamentally new.
Small incremental improvements is all you get with mature products (with very rare exceptions). That's true for processors, mobile phones, airplanes, ...
ejeffrey
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #2 on: July 25, , 03:18:53 pm »
The big deal with the RFSoC was including a ton of high speed data converters on the same chip. This makes it extremely attractive for custom data acquisition devices, high performance SDR, and similar applications.
The MPSoC is basically just a bigger zynq. It has a multi core 64 bit arm CPU, and it also has a dedicated cortex-R processor for realtime and fault tolerant applications. But the people I know who use them don't really care about those features, the main thing is the much bigger and higher performance programmable logic with many more and faster high speed transceivers. For instance some versions of the MPSoC can support 4 100 gigabit Ethernet ports. It's also got more bram, UltraRAM (high density psuedo dual port memory) and more DSP resources.
glenenglish
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #3 on: July 25, , 09:23:49 pm »
Ultrascale+ parts like MPSoC are revolutionary, compared to 7 series Zynq.
With Ultrascale+, you can utilize, (depending on the design) right up to 99% before they slow down. Compare to 7 series that slow down at > ~ 70% (design dependent). They are awesome.
and the fabric is fast --even in the slowest parts, 650 MHz+ multipliers....
The dual core R5 can run lockstep and is in its own power domain. The R5 is not just another ARM cortex M, it is a processor that can unwind itself out of trouble, out of aborts, sorts out instructions half executed etc, it is design to keep on trucking
With all this comes a great deal of complexity. beware of this ! You could learn every about MPSoC and it might take you a lifetime.
You can spend a year reading the datasheets thoroughly. And, you want a simple watchdog ? then you better get to know and write custom firmware for the PMU !
But Altera 10nm Agilex 5 with HPS ( in midrange 50k-300k) will go head to head and beyond later this year in production.... Unless you need to go to market now, I think Agilex5 is worth waiting for.
RFSoC is fantastic, but IMO is only useful when you need half a dozen 5GHz converters, and their dynamic performance is not particularly good at < 500 MHz compared to say, a $35 12 bit 250 MHz converter, but they are not designed to compete in that region. they compete in the 1-10 GHz large instantaneous BW region.
7 series ZYNQ still holds the market sweetspot below then 50k LE region though, and small 225 and 400 0.8mm ball packages
Other notable SoC options are Microchip Polarfire SoC , Efinix Titanium SoC, . Forget Cyclone IV SOC.. ROFL.
« Last Edit: July 25, , 09:31:32 pm by glenenglish »
matrixofdynamism
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #4 on: July 26, , 09:35:25 am »
Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.
So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.
asmi
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #5 on: July 26, , 02:49:44 pm »
Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.
So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.
Easy - PL is to perform the primary function of a device, and PS is to run the HMI (GUI, peripherals, etc.). A lot of devices require APU to run the HMI in addition to the main FPGA which does the processing. Combining these into the single chip has a lot of advantages - smaller PCBs, less power consumption, easier routing, etc. If only these MPSoCs wouldn't cost so much, they would be a no-brainer for a lot of applications.
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KE5FX
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #6 on: July 26, , 08:06:03 pm »
You tend to see the SoCs used in MIMO applications like cellular base station transceivers, or in high-end radar work where cost is no object. For everything else, it is usually going to be cheaper to hook your own choice of ADCs and DACs up to your own choice of FPGA and controller hardware.
At least that's been the case historically.
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radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #7 on: July 27, , 02:13:11 am »
RFSoC's big advantage relative to a big FPGA coupled to high speed converters is that the interface between the two (in the latter case) is non-trivial. Even with standardization like JESD204B, it's really hard to get right even when using someone else's known working boards. Integrating the converters on chip means you have direct access to the parallel data stream without a complex SERDES in between. The drawback is that the converters can have noise coupling in from the digital part of the SoC. They are also really expensive.
ejeffrey
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #8 on: July 27, , 04:47:31 pm »
An RFSoC in volume direct from Xilinx is actually competitive with stand alone FPGA + high speed data converters. And for low volumes, the eval boards are not exactly cheap (~$15k), but are a real bargain considering what you get and what it would cost to get an equivalent.
In addition, the interconnect bandwidth is higher. Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited. Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.
Of course in addition to possible noise, a limitation of the RFSoC is that you only get the configurations xilinx makes. If it's overkill for your needs you don't get a discount, while if it's not sufficient it won't work.
radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #9 on: July 27, , 05:27:09 pm »
An additional concern with JESD204 is that if you change the sample rate (or interpolation/decimation config for converters that support it), one must go through a lengthy retraining and re-syncing sequence. With the older (external) parallel converters, this was not usually a concern. I haven't worked with an RFSOC yet (too expensive!) but I imagine it will be similar in this regard.
To be fair, most applications such as cell base-stations or radar transceivers don't require frequent sample rate changes. Oscilloscope digitizers would need this ability, though.
In addition, the interconnect bandwidth is higher. Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited. Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.
There are some rather impressive parts like the ADC08DJRF that can do 10.4 GSPS without internal decimation, but require eight JESD204 lanes at 17 Gbps for a single channel. The newer RFSOCs now include hard-IP digital downconverters. Most communications/radio applications for such devices would use a DUC/DDC anyway so it's not much of a loss.
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glenenglish
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #10 on: July 27, , 09:25:25 pm »
I have worked with RFSoC parts. Fantastic for specific jobs. If you are worried about cost, then you are trying to use it in the wrong market.
IMO, they're only cost effective compared to multiple 5Gsps converters, and the spurs in the passb relegate it to wideband functions, as the SFDR isnt really all that great for any high dynamic range narrowband application, and the sampling clocks are polluted.
There's another aspect for their use - and that is link power consumption
as radar_macgyver says, high speed external DCs , they chew up JESD lanes like nothing else. That has a power cost and silicon area cost to get between the DC and the FPGA. extra pain avoided by one package.
For the ADC side - If used as a back end , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications (wideband, lots if computation) and cellular base stations. Both are relatively low dynamic range applications.
When the fabric multipliers run at 650 MHz and you are filtering a signal (say a wideband correlator ) at 5 Gsps, you chew up multipliers and rams big time.... A 100 tap non symmetrical fir is going to chew multipliers ! LOL.
« Last Edit: July 27, , 09:29:36 pm by glenenglish »
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radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #11 on: July 28, , 01:15:35 am »
For the ADC side - If used as a back end , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications (wideband, lots if computation) and cellular base stations. Both are relatively low dynamic range applications.
(emphasis mine)
Spot on - my usual radar applications are the opposite (relatively narrow-band, very high dynamic range). I'm curious what the applications of wideband radar are, if you're allowed to share (the only one that comes to mind is ground-penetrating radar). For narrowband (or indeed, multiple narrowband channels, typical of basestation applications), an off-chip converter with integrated DDCs would be significantly lower cost. Power consumption increase due to the JESD204 lanes and their associated transceivers will likely be offset by the thousands of DSP blocks!
matrixofdynamism
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #12 on: August 01, , 01:17:59 pm »
FPGAs are themself not ubiquitous like ARM based cores or other microprocessor, microcontroller and DSPs. However, it seems that even within the FPGA domain, the RFSoC and MPSoC are for niche applications. The demand must be high enough that Xilinx went ahead and created such devices.
What I have understood is that the integrated data converters are a huge plus. But what about the multicore ARM processors of different types that exist? How would I harness them?
Also, I believe that some other companies (Maybe Microchip) have come with this idea to have a small amount of programmable logic in their microcontrollers. Has anyone used these type of tools at all?
DutchGert
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #13 on: November 17, , 04:06:12 pm »
These parts are perfect and very impressive if you can use them for our specific use case.
Back in I did a project with the original Zync for a, relatively basic, camera - monitor system in automotive.
It has MIPI in and outputs so you can interface camera and display SerDes devices.
Then, you use the FPGA part for all the parallel image processing and the ARM cores for drawing up a GUI etc.
Few years later, we used the MPSoC for the second generation of this product.
So, we had a big ECU with 6 camera inputs, 3, display outputs, it would do basic object detection (is there someone in the dead corner of my truck, am i still following the road lines etc), do both the video processing, GUI, object detection and vehicle communication with one single chip and, best of all, all of this functional safe and some parts in lockstep.
These parts are really nice. And guess what, they might be on Digikey for USD a pop but we paid around 20 bucks each for them in (big) volume.
The RFSoC is one of the devices I have wanted to get my hands on, ever since its announcement. So I was very excited to find a ZCU111 RFSoC development board waiting for me when I recently returned from Linaro Connect.
For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs — making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc.
The ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVGE RFSoC that provides:
- Eight 4 GSPS 12-bit RF ADC
- Eight 6.5 GSPS 14-bit RF DAC
- Eight Soft Decision Forward Error Correction (SD-FEC)
To enable users to prototype a range of solutions, the ZCU111 also offers a range of interfacing capabilities including Ethernet, SFP28 Cages, SATA, USB3, and high pin count FMC for additional flexibility. Of course, with a device like the RFSoC moving data on and off the board at high speed is critical, hence the range of different high speed connectivity options.
As the RFSoC enables complex single device solutions, the ZCU111 also features two banks of DDR 4, each bank is 4GB. One bank is connected to the PS, while the second is connected to the PL. The 4GB connected to the PS enables operating systems such as Linux to be used to implement higher levels of the applications, e.g. communication, system management, security, and adaption. While the DDR bank connected to the PL can be used in the signal processing path.
The most important element of the ZCU111, though, is how we connect the RF ADCs and RF DACs within the RFSoC to the outside world. This is made possible through two RFMC connectors — one connector provides RF output, the other RF inputs.
Rather helpfully, the ZCU111 is provided with a Balun board which connects to both of these interfaces. Along with providing the Baluns that convert between differential and single ended signaling, this board is equipped with multiple SMA connectors for RF input and output.
Once I had unpacked the board, I read the supporting information online about the ZCU111 and its configuration. The first thing I wanted to do was a loop back test using two DACs to stimulate two ADCs. We can do this physically with the Balun board, and rather useful, the ZCU111 also comes with a Targeted Reference Design (TRD) which enables us to configure the RFSoC ADCs and DACs to do just that (and more as we will see in future blogs).
To get the example up and running, we need to create an SD card which contains the TRD image and also install the RF Data Converter Evaluation User Interface GUI on a PC. This GUI allows us to communicate with the RFSoC over Ethernet and configure both clocking and the DAC and ADC tiles. This GUI also lets us generate simple signals and examine the received spectrum, exactly what we want.
For this simple example using the GUI, I configured the RFSoC to use two of the DACs available in DAC tile one for signal generation. I also configured the RFSoC to use the ADCs available in ADC tile one to receive the generated signals.
The first step in doing this is to correctly configure the DACs as follows:
Sample clock = .76 MHz
Crossbar I & Q, Interpolation x8, Decoder Mode High Linearity and Mixer Frequency of MHz.
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The second step is to configure the ADC in tile one, which can be done as follows:
Sample Clock = .88 MHz
Decimation x4, Mixer Frequency - MHz
With both the ADC and DAC configured, the next step is to create stimulus for the ADC using the DAC.
We do this on the signal generation tab, which is available for each DAC. In this tab, we can enter a Center Frequency. The image below shows a CF of 150 MHz.
For this example, I used Center Frequencies of 150 MHz and 200 MHz.
With the stimulus being generated, I was then able to monitor the ADC signals using the acquisition function. The acquisition function allows the received signal to be examined in either the time or frequency domain.
For most applications, the frequency domain view is the most suitable and provides the most information on the converter and system performance.
With both DACs generating signals with CF at 150 MHz and 200 MHz, the plots below show the received data.
These plots show the base band signal at 100 MHz and 150 MHz. These are the frequencies as would be expected as the lower side band is reduced by MHz in the ADC channel.
At the DAC output, this lower side band would be at either MHz or MHz depending upon the setting of Center Frequency.
As you can see, both ADC channels capture the signal at the expected location in the received frequency domain.
If you want to see the example in action I took a simple video while setting up the examples.
This is a really great board and device and I cannot wait to do more with it over the coming weeks and months.
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