What are the different types of integrated circuit packages?

Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.

Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.

Through-hole packages

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Through-hole technology uses holes drilled through the printed circuit board (PCB) for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.

Three 14-pin (DIP14) plastic dual in-line packages containing IC chips.

Surface mount

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Acronym Full name Remark CCGA Ceramic column-grid array (CGA)[3] CGA Column-grid array[3] CERPACK Ceramic package[4] CQGP[5] LLP Lead-less lead-frame package A package with metric pin distribution (0.5–0.8 mm pitch)[6] LGA Land grid array[3] LTCC Low-temperature co-fired ceramic[7] MCM Multi-chip module[8] MICRO SMDXT Micro surface-mount device extended technology[9]

Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.

Chip carrier

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A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.

Acronym Full name Remark BCC Bump chip carrier[3] CLCC Ceramic lead-less chip carrier[1] LCC Lead-less chip carrier[3] Contacts are recessed vertically. LCC Leaded chip carrier[3] LCCC Leaded ceramic-chip carrier[3] DLCC Dual lead-less chip carrier (ceramic)[3] PLCC Plastic leaded chip carrier[1][3]

Pin grid arrays

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Acronym Full name Remark OPGA Organic pin-grid array FCPGA Flip-chip pin-grid array[3] PAC Pin array cartridge[10] PGA Pin-grid array Also known as PPGA[1] CPGA Ceramic pin-grid array[3]

Flat packages

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Small outline packages

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A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs.

Acronym Full name Remark SOP Small-outline package[1] CSOP Ceramic small-outline package DSOP Dual small-outline package HSOP Thermally-enhanced small-outline package HSSOP Thermally-enhanced shrink small-outline package[16] HTSSOP Thermally-enhanced thin shrink small-outline package[16] mini-SOIC Mini small-outline integrated circuit MSOP Mini small-outline package Maxim uses the trademarked name µMAX for MSOP packages PSOP Plastic small-outline package[3] PSON Plastic small-outline no-lead package QSOP Quarter-size small-outline package The terminal pitch is 0.635 mm.[3] SOIC Small-outline integrated circuit Also known as SOIC NARROW and SOIC WIDE SOJ Small-outline J-leaded package SON Small-outline no-lead package SSOP Shrink small-outline package[3] TSOP Thin small-outline package[3] TSSOP Thin shrink small-outline package[3] TVSOP Thin very-small-outline package[3] VSOP Very-small-outline package[16] VSSOP Very-thin shrink small-outline package[16] Also referred as MSOP = micro small-outline package WSON Very-very-thin small-outline no-lead package USON Very-very-thin small-outline no-lead package Slightly smaller than WSON

Chip-scale packages

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According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. Chip-scale package

Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown (top) for comparison.

Ball grid array

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Ball grid array (BGA) uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.[1][3]

Acronym Full name Remark FBGA Fine-pitch ball-grid array A square or rectangular array of solder balls on one surface[3] LBGA Low-profile ball-grid array Also known as laminate ball-grid array[3] TEPBGA Thermally-enhanced plastic ball-grid array CBGA Ceramic ball-grid array[3] OBGA Organic ball-grid array[3] TFBGA Thin fine-pitch ball-grid array[3] PBGA Plastic ball-grid array[3] MAP-BGA Mold array process - ball-grid array [1] UCSP Micro (μ) chip-scale package Similar to a BGA (A Maxim trademark example)[18] μBGA Micro ball-grid array Ball spacing less than 1 mm LFBGA Low-profile fine-pitch ball-grid array[3] TBGA Thin ball-grid array[3] SBGA Super ball-grid array[3] Above 500 balls UFBGA Ultra-fine ball-grid array[3]

Transistor, diode, small-pin-count IC packages

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A drawing of a ZN414 IC in a TO-18 package

• MELF: Metal electrode leadless face (usually for resistors and diodes)
• SOD: Small-outline diode.
• SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
• TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
  • TO-3: Panel-mount with leads
  • TO-5: Metal can package with radial leads
  • TO-18: Metal can package with radial leads
  • TO-39
  • TO-46
  • TO-66: Similar shape to the TO-3 but smaller
  • TO-92: Plastic-encapsulated package with three leads
  • TO-99: Metal can package with eight radial leads
  • TO-100
  • TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
  • TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
  • TO-226[24]
  • TO-247:[25] Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
  • TO-251:[25] Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting
  • TO-252:[25] (also called SOT428, DPAK):[25] SMT package similar to the DPAK but smaller
  • TO-262:[25] Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting
  • TO-263:[25] Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole
  • TO-274:[25] Also called Super-247: SMT package similar to the TO-247 without the mounting hole

Dimension reference

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A general surface mount chip, with major dimensions.

C

Clearance between IC body and PCB

H

Total height

T

Lead thickness

L

Total carrier length

LW

Lead width

LL

Lead length

P

Pitch

A general through-hole pin chip, with major dimensions.

C

Clearance between IC body and board

H

Total height

T

Lead thickness

L

Total carrier length

LW

Lead width

LL

Lead length

P

Pitch

WB

IC body width

WL

Lead-to-lead width

Package dimensions

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All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

C

Clearance between package body and PCB.

H

Height of package from pin tip to top of package.

T

Thickness of pin.

L

Length of package body only.

LW

Pin width.

LL

Pin length from package to pin tip.

P

Pin pitch (distance between conductors to the PCB).

WB

Width of the package body only.

WL

Length from pin tip to pin tip on the opposite side.

Dual row

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Image Family Pin Name Package L WB WL H C P LL T LW DIP Y Dual inline package 8-DIP 9.2–9.8 6.2–6.48 7.62 7.7 2.54 (0.1

 

in) 3.05–3.6 1.14–1.73 32-DIP 15.24 2.54 (0.1

 

in) LFCSP N Lead-frame chip-scale package 0.5 MSOP Y Mini small-outline package 8-MSOP 3 3 4.9 1.1 0.10 0.65 0.95 0.18 0.17–0.27 10-MSOP 3 3 4.9 1.1 0.10 0.5 0.95 0.18 0.17–0.27 16-MSOP 4.04 3 4.9 1.1 0.10 0.5 0.95 0.18 0.17–0.27 SO
SOIC
SOP Y Small-outline integrated circuit 8-SOIC 4.8–5.0 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 14-SOIC 8.55–8.75 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 16-SOIC 9.9–10 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 16-SOIC 10.1–10.5 7.5 10.00–10.65 2.65 0.10–0.30 1.27 1.4 0.23–0.32 0.38–0.40 SOT Y Small-outline transistor SOT-23-6 2.9 1.6 2.8 1.45 0.95 0.6 0.22–0.38 SSOP Y Shrink small-outline package 0.65 TDFN N Thin dual flat no-lead 8-TDFN 3 3 3 0.7–0.8 0.65 — 0.19–0.3 TSOP Y Thin small-outline package 0.5 TSSOP Package TSSOP Y Thin shrink small-outline package 8-TSSOP[26] 2.9-3.1 4.3-4.5 6.4 1.2 0.15 0.65 0.09–0.2 0.19–0.3 Y 14-TSSOP[27] 4.9-5.1 4.3-4.5 6.4 1.1 0.05-0.15 0.65 0.09-0.2 0.19-0.30 20-TSSOP[28] 6.4-6.6 4.3-4.5 6.4 1.1 .05-0.15 0.65 0.09-0.2 0.19-0.30 µSOP Y Micro small-outline package[29] µSOP-8 3 4.9 1.1 0.65 US8[30] Y US8 package 2 2.3 3.1 .7 0.5

Quad rows

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Image Family Pin Name Package WB WL H C L P LL T LW PLCC N Plastic leaded chip-carrier 1.27 CLCC N Ceramic leadless chip-carrier 48-CLCC 14.22 14.22 2.21 14.22 1.016 — 0.508 LQFP Y Low-profile quad flat package 0.50 TQFP Y Thin quad flat-package TQFP-44 10.00 12.00 0.35–0.50 0.80 1.00 0.09–0.20 0.30–0.45 TQFN N Thin quad flat no-lead

LGA

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Package x y z 52-ULGA 12

 

mm 17

 

mm 0.65

 

mm 52-ULGA 14

 

mm 18

 

mm 0.10

 

mm 52-VELGA ? ? ?

Multi-chip packages

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A variety of techniques for interconnecting several chips within a single package have been proposed and researched:

By terminal count

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Example of component sizes, metric and imperial codes and comparison included Composite image of a 11×44 LED matrix lapel name tag display using 1608/0603-type SMD LEDs. Top: A little over half of the 21×86 mm display. Center: Close-up of LEDs in ambient light. Bottom: LEDs in their own red light. SMD capacitors (on the left) with two through-hole capacitors (on the right)

Surface-mount components are usually smaller than their counterparts with leads, and are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes (the leading standardisation body is JEDEC).

The codes given in the chart below usually tell the length and width of the components in tenths of millimeters or hundredths of inches. For example, a metric 2520 component is 2.5 mm by 2.0 mm which corresponds roughly to 0.10 inches by 0.08 inches (hence, imperial size is 1008). Exceptions occur for imperial in the two smallest rectangular passive sizes. The metric codes still represent the dimensions in mm, even though the imperial size codes are no longer aligned. Problematically, some manufacturers are developing metric 0201 components with dimensions of 0.25 mm × 0.125 mm (0.0098 in × 0.0049 in),[32] but the imperial 01005 name is already being used for the 0.4 mm × 0.2 mm (0.0157 in × 0.0079 in) package. These increasingly small sizes, especially 0201 and 01005, can sometimes be a challenge from a manufacturability or reliability perspective.[33]

Two-terminal packages

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Rectangular passive components

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Mostly resistors and capacitors.

Package Approximate dimensions, length × width Typical resistor
power rating (W) Metric Imperial 0201 008004 0.25 mm × 0.125 mm 0.010 in × 0.005 in 03015 009005 0.3 mm × 0.15 mm 0.012 in × 0.006 in 0.02[34] 0402 01005 0.4 mm × 0.2 mm 0.016 in × 0.008 in 0.031[35] 0603 0201 0.6 mm × 0.3 mm 0.02 in × 0.01 in 0.05[35] 1005 0402 1.0 mm × 0.5 mm 0.04 in × 0.02 in 0.062[36]–0.1[35] 1608 0603 1.6 mm × 0.8 mm 0.06 in × 0.03 in 0.1[35] 2012 0805 2.0 mm × 1.25 mm 0.08 in × 0.05 in 0.125[35] 2520 1008 2.5 mm × 2.0 mm 0.10 in × 0.08 in 3216 1206 3.2 mm × 1.6 mm 0.125 in × 0.06 in 0.25[35] 3225 1210 3.2 mm × 2.5 mm 0.125 in × 0.10 in 0.5[35] 4516 1806 4.5 mm × 1.6 mm 0.18 in × 0.06 in[37] 4532 1812 4.5 mm × 3.2 mm 0.18 in × 0.125 in 0.75[35] 4564 1825 4.5 mm × 6.4 mm 0.18 in × 0.25 in 0.75[35] 5025 2010 5.0 mm × 2.5 mm 0.20 in × 0.10 in 0.75[35] 6332 2512 6.3 mm × 3.2 mm 0.25 in × 0.125 in 1[35] 6863 2725 6.9 mm × 6.3 mm 0.27 in × 0.25 in 3 7451 2920 7.4 mm × 5.1 mm 0.29 in × 0.20 in[38]

Tantalum capacitors

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Package Dimensions (Length, typ. × width, typ. × height, max.) EIA 2012-12 (KEMET R, AVX R) 2.0 mm × 1.3 mm × 1.2 mm EIA 3216-10 (KEMET I, AVX K) 3.2 mm × 1.6 mm × 1.0 mm EIA 3216-12 (KEMET S, AVX S) 3.2 mm × 1.6 mm × 1.2 mm EIA 3216-18 (KEMET A, AVX A) 3.2 mm × 1.6 mm × 1.8 mm EIA 3528-12 (KEMET T, AVX T) 3.5 mm × 2.8 mm × 1.2 mm EIA 3528-21 (KEMET B, AVX B) 3.5 mm × 2.8 mm × 2.1 mm EIA 6032-15 (KEMET U, AVX W) 6.0 mm × 3.2 mm × 1.5 mm EIA 6032-28 (KEMET C, AVX C) 6.0 mm × 3.2 mm × 2.8 mm EIA 7260-38 (KEMET E, AVX V) 7.2 mm × 6.0 mm × 3.8 mm EIA 7343-20 (KEMET V, AVX Y) 7.3 mm × 4.3 mm × 2.0 mm EIA 7343-31 (KEMET D, AVX D) 7.3 mm × 4.3 mm × 3.1 mm EIA 7343-43 (KEMET X, AVX E) 7.3 mm × 4.3 mm × 4.3 mm

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Aluminum capacitors

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Package Dimensions (Length, typ. × width, typ. × height, max.) Cornell-Dubilier A 3.3 mm × 3.3 mm × 5.5 mm Chemi-Con D 4.3 mm × 4.3 mm × 5.7 mm Panasonic B 4.3 mm × 4.3 mm × 6.1 mm Chemi-Con E 5.3 mm × 5.3 mm × 5.7 mm Panasonic C 5.3 mm × 5.3 mm × 6.1 mm Chemi-Con F 6.6 mm × 6.6 mm × 5.7 mm Panasonic D 6.6 mm × 6.6 mm × 6.1 mm Panasonic E/F, Chemi-Con H 8.3 mm × 8.3 mm × 6.5 mm Panasonic G, Chemi-Con J 10.3 mm × 10.3 mm × 10.5 mm Chemi-Con K 13 mm × 13 mm × 14 mm Panasonic H 13.5 mm × 13.5 mm × 14 mm Panasonic J, Chemi-Con L 17 mm × 17 mm × 17 mm Panasonic K, Chemi-Con M 19 mm × 19 mm × 17 mm

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Small-outline diode (SOD)

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Package Dimensions (Length, typ. × width, typ. × height, max.) SOD-80C 3.5 mm × ⌀ 1.5 mm[44] SOD-123 2.65 mm × 1.6 mm × 1.35 mm[45] SOD-128 3.8 mm × 2.5 mm × 1.1 mm[46] SOD-323 (SC-76) 1.7 mm × 1.25 mm × 1.1 mm[47] SOD-523 (SC-79) 1.2 mm × 0.8 mm × 0.65 mm[48] SOD-723 1.0 mm × 0.6 mm × 0.65 mm[49] SOD-923 0.8 mm × 0.6 mm × 0.4 mm[50]

Metal electrode leadless face (MELF)

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Mostly resistors and diodes; barrel shaped components, dimensions do not match those of rectangular references for identical codes.[51]

Package Dimensions
Typical resistor rating Power (W) Voltage (V) MicroMELF (MMU), 0102 2.2 mm × ⌀ 1.1 mm 0.2–0.3 150 MiniMELF (MMA), 0204 3.6 mm × ⌀ 1.4 mm 0.25–0.4 200 MELF (MMB), 0207 5.8 mm × ⌀ 2.2 mm 0.4–1.0 300

Commonly used for rectifier, Schottky, and other diodes.

Package Dimensions (incl. leads) (Length, typ. × width, typ. × height, max.) DO-214AA (SMB) 5.4 mm × 3.6 mm × 2.65 mm[52] DO-214AB (SMC) 7.95 mm × 5.9 mm × 2.25 mm[52] DO-214AC (SMA) 5.2 mm × 2.6 mm × 2.15 mm[52]

Three- and four-terminal packages

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Small-outline transistor (SOT)

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Package Aliases Dimensions (excl. leads) (Length, typ. × width, typ. × height, max.) Number of terminals Remark SOT-23-3 TO-236-3, SC-59 2.92 mm × 1.3 mm × 1.12 mm[53] 3 SOT-89 TO-243,[54] SC-62[55] 4.5 mm × 2.5 mm × 1.5 mm[56] 4 Center pin is connected to a large heat-transfer pad SOT-143 TO-253 2.9 mm × 1.3 mm × 1.22 mm[57] 4 Tapered body, one larger pad denotes terminal 1 SOT-223 TO-261 6.5 mm × 3.5 mm × 1.8 mm[58] 4 One terminal is a large heat-transfer pad SOT-323 SC-70 2 mm × 1.25 mm × 1.1 mm[59] 3 SOT-416 SC-75 1.6 mm × 0.8 mm × 0.9 mm[60] 3 SOT-663 1.6 mm × 1.2 mm × 0.6 mm[61] 3 SOT-723 1.2 mm × 0.8 mm × 0.55[62] 3 Has flat leads SOT-883 SC-101 1 mm × 0.6 mm × 0.5 mm[63] 3 Is lead-less

Other

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• DPAK (TO-252, SOT-428): Discrete Packaging. Developed by Motorola to house higher powered devices. Comes in three[64] or five-terminal[65] versions.
• D2PAK (TO-263, SOT-404): Bigger than the DPAK; basically a surface mount equivalent of the TO220 through-hole package. Comes in 3, 5, 6, 7, 8 or 9-terminal versions.[66]
• D3PAK (TO-268): Even larger than D2PAK.[67][68]

Five- and six-terminal packages

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Small-outline transistor (SOT)

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Package Aliases Dimensions (excl. leads) (Length, typ. × width, typ. × height, max.) Number of terminals Leaded or leadless SOT-23-6 SOT-26, SC-74 2.9 mm × 1.3 mm × 1.3 mm[69] 6 Leaded SOT-353 SC-88A 2 mm × 1.25 mm × 0.95 mm[70] 5 Leaded SOT-363 SC-88, SC-70-6 2 mm × 1.25 mm × 0.95 mm[71] 6 Leaded SOT-563 1.6 mm × 1.2 mm × 0.6 mm[72] 6 Leaded SOT-665 1.6 mm × 1.6 mm × 0.55 mm[73] 5 Leaded SOT-666 1.6 mm × 1.2 mm × 0.6 mm[74] 6 Leaded SOT-886 1.45 mm × 1 mm × 0.5 mm[75] 6 Leadless SOT-891 1 mm × 1 mm × 0.5 mm[76] 6 Leadless SOT-953 1 mm × 0.8 mm × 0.5 mm[77] 5 Leaded SOT-963 1 mm × 1 mm × 0.5 mm[78] 6 Leaded SOT-1115 1 mm × 0.9 mm × 0.35 mm[79] 6 Leadless SOT-1202 1 mm × 1 mm × 0.35 mm[80] 6 Leadless Various SMD chips, desoldered MLP package 28-pin chip, upside down to show contacts

Packages with more than six terminals

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• Plastic leaded chip carrier (PLCC): square, J-lead, pin spacing 1.27 mm
• Quad flat package (QFP): various sizes, with pins on all four sides
• Low-profile quad flat-package (LQFP): 1.4 mm high, varying sized and pins on all four sides
• Plastic quad flat-pack (PQFP), a square with pins on all four sides, 44 or more pins
• Ceramic quad flat-pack (CQFP): similar to PQFP
• Metric quad flat-pack (MQFP): a QFP package with metric pin distribution
• Thin quad flat-pack (TQFP), a thinner version of LQFP
• Quad flat no-lead (QFN): smaller footprint than leaded equivalent
• Leadless chip carrier (LCC): contacts are recessed vertically to "wick-in" solder. Common in aviation electronics because of robustness to mechanical vibration.
• Micro leadframe package (MLP, MLF): with a 0.5 mm contact pitch, no leads (same as QFN)
• Power quad flat no-lead (PQFN): with exposed die-pads for heatsinking

Grid arrays

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Non-packaged devices

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Although surface-mount, these devices require specific process for assembly.

• Chip-on-board (COB), a bare silicon chip, that is usually an integrated circuit, is supplied without a package (which is usually a lead frame overmolded with epoxy) and is attached, often with epoxy, directly to a circuit board. The chip is then wire bonded and protected from mechanical damage and contamination by an epoxy "glob-top".
• Chip-on-flex (COF), a variation of COB, where a chip is mounted directly to a flex circuit. Tape-automated bonding process is also a chip-on-flex process as well.
• Chip-on-glass (COG), a variation of COB, where a chip, typically a liquid crystal display (LCD) controller, is mounted directly on glass.
• Chip-on-wire (COW), a variation of COB, where a chip, typically a LED or RFID chip, is mounted directly on wire, thus making it a very thin and flexible wire. Such wire may then be covered with cotton, glass or other materials to make into smart textiles or electronic textiles.

There are often subtle variations in package details from manufacturer to manufacturer, and even though standard designations are used, designers need to confirm dimensions when laying out printed circuit boards.

See also

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References

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Final stage of semiconductor device fabrication

This article is about the final stage in the manufacturing process of integrated circuits. For an article about the physical enclosure that surrounds integrated circuits, see Semiconductor package

Cross section of a dual in-line package. This type of package houses a small semiconducting die, with microscopic wires attaching the die to the lead frames, allowing for electrical connections to be made to a PCB. Dual in-line (DIP) integrated circuit metal lead frame tape with contacts

Integrated circuit packaging is the final stage of semiconductor device fabrication, in which the die is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

The packaging stage is followed by testing of the integrated circuit.

Design considerations

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Various IC packages (left to right): TSSOP-32, TQFP-100, SO-20, SO-14, SSOP-28, SSOP-16, SO-8, QFN-28

Electrical

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The current-carrying traces that run out of the die, through the package, and into the printed circuit board (PCB) have very different electrical properties compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself. Therefore, it is important that the materials used as electrical contacts exhibit characteristics like low resistance, low capacitance and low inductance.[1] Both the structure and materials must prioritize signal transmission properties, while minimizing any parasitic elements that could negatively affect the signal.

Controlling these characteristics is becoming increasingly important as the rest of technology begins to speed up. Packaging delays have the potential to make up almost half of a high-performance computer's delay, and this bottleneck on speed is expected to increase.[1]

Mechanical and thermal

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The integrated circuit package must resist physical breakage, keep out moisture, and also provide effective heat dissipation from the chip. Moreover, for RF applications, the package is commonly required to shield electromagnetic interference, that may either degrade the circuit performance or adversely affect neighboring circuits. Finally, the package must permit interconnecting the chip to a PCB.[1] The materials of the package are either plastic (thermoset or thermoplastic), metal (commonly Kovar) or ceramic. A common plastic used for this is epoxy-cresol-novolak (ECN).[2] All three material types offer usable mechanical strength, moisture and heat resistance. Nevertheless, for higher-end devices, metallic and ceramic packages are commonly preferred due to their higher strength (which also supports higher pin-count designs), heat dissipation, hermetic performance, or other reasons. Generally, ceramic packages are more expensive than similar plastic packages.[3]

Some packages have metallic fins to enhance heat transfer, but these take up space. Larger packages also allow for more interconnecting pins.[1]

Economic

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Cost is a factor in selection of integrated circuit packaging. Typically, an inexpensive plastic package can dissipate heat up to 2W, which is sufficient for many simple applications, though a similar ceramic package can dissipate up to 50W in the same scenario.[1] As the chips inside the package get smaller and faster, they also tend to get hotter. As the subsequent need for more effective heat dissipation increases, the cost of packaging rises along with it. Generally, the smaller and more complex the package needs to be, the more expensive it is to manufacture.[3] Wire bonding can be used instead of techniques such as flip-chip to reduce costs.[4]

History

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Small-outline integrated circuit. This package has 16 "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.

Early integrated circuits were packaged in ceramic flat packs, which the military used for many years for their reliability and small size. The other type of packaging used in the 1970s, called the ICP (Integrated Circuit Package), was a ceramic package (sometimes round as the transistor package), with the leads on one side, co-axially with the package axis.

Commercial circuit packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in plastic.[5] In the 1980s VLSI pin counts exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages.[6] Surface mount packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-outline integrated circuit—a carrier which occupies an area about 30–50% less than an equivalent DIP, with a typical thickness that is 70% less.[6]

Early USSR-made integrated circuit. The tiny block of semiconducting material (the "die"), is enclosed inside the round, metallic case (the "package").

The next big innovation was the area array package, which places the interconnection terminals throughout the surface area of the package, providing a greater number of connections than previous package types where only the outer perimeter is used. The first area array package was a ceramic pin grid array package.[1] Not long after, the plastic ball grid array (BGA), another type of area array package, became one of the most commonly used packaging techniques.[7]

In the late 1990s, plastic quad flat pack (PQFP) and thin small-outline packages (TSOP) replaced PGA packages as the most common for high pin count devices,[1] though PGA packages are still often used for microprocessors. However, industry leaders Intel and AMD transitioned in the 2000s from PGA packages to land grid array (LGA) packages.[8]

Ball grid array (BGA) packages have existed since the 1970s, but evolved into flip-chip ball grid array (FCBGA) packages in the 1990s. FCBGA packages allow for much higher pin count than any existing package types. In an FCBGA package, the die is mounted upside-down (flipped) and connects to the package balls via a substrate that is similar to a printed-circuit board rather than by wires. FCBGA packages allow an array of input-output signals (called Area-I/O) to be distributed over the entire die rather than being confined to the die periphery.[9] Ceramic subtrates for BGA were replaced with organic substrates to reduce costs and use existing PCB manufacturing techniques to produce more packages at a time by using larger PCB panels during manufacturing.[10]

Traces out of the die, through the package, and into the printed circuit board have very different electrical properties, compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself.

Recent developments consist of stacking multiple dies in single package called SiP, for System In Package, or three-dimensional integrated circuit. Combining multiple dies on a small substrate, often ceramic, is called an MCM, or Multi-Chip Module. The boundary between a big MCM and a small printed circuit board is sometimes blurry.[11]

Common package types

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Left is X-ray of right PCB , showing metal lead frames inside IC packages

Operations

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After wafer dicing, the die is picked from the diced wafer using a vaccum tip or suction cup[12][13] and undergoes die attachment which is the step during which a die is mounted and fixed to the package or support structure (header).[14] In high-powered applications, the die is usually eutectic bonded onto the package, using e.g. gold-tin or gold-silicon solder (for good heat conduction). For low-cost, low-powered applications, the die is often glued directly onto a substrate (such as a printed wiring board) using an epoxy adhesive. Alternatively dies can be attached using solder. These techniques are usually used when the die will be wire bonded; dies with flip chip technology do not use these attachment techniques.[15][16]

The following operations are performed at the packaging stage, as broken down into bonding, encapsulation, and wafer bonding steps. Note that this list is not all-inclusive and not all of these operations are performed for every package, as the process is highly dependent on the package type.

See also

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References

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