Hello, I am using the RFSoC 4x2 with PYNQ, and I’m having some trouble generating some of the waveforms which I want to. Using the loopback method shown in the tutorial RFDC notebook, I want to get started with generating a simple pulse – however, I’m not sure how to transmit a variable waveform. All of the example notebooks used a fixed waveform, where the frequency of the transmission was set before the receiver was set up. However, for something like a pulsed or frequency modulated wave, I will need to have this transmitter waveform change while the receiver is enabled. Can anyone point me in the right direction? Thanks, any help is appreciated.
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Hi ak123,
Welcome to the forums!
It sounds like you want to create a signal generator that responds (in some way) to a signal received by the RF ADC. Does this sound correct?
I am interested in this too. In particular, I would like to create a generalised framework for others (such as yourself) to generate their custom waveforms based on feedback from the RF ADC.
Could I ask a few questions?
To answer your question, I am unaware of anything out of the box that will do what you are describing. You will need to design a custom FPGA architecture that can respond correctly to received waveforms (from the RF ADC) and feedback information to the signal generation stage (to the RF DAC).
I’d like to explore this problem further, and the questions above would help me a lot here and hopefully give you back something useful in the future,
Thanks,
David.
Hi David,
Sorry for the confusion regarding the “loopback method”, I don’t think that’s quite what I meant. I did not mean to imply having a system where the DAC transmitter depends on the ADC receiver.
Although that does sound like an interesting problem, I am not quite there yet – I just want to be able to generate different types of waveforms from the DAC, independent of the ADC. For simplicity’s sake, I would just want to be able to connect the ADC to the DAC directly with a SMA connector for now (rather than using separate transmitter/receiver antennas).
From what I understand, in the example notebooks, we are just generating continuous wave waveforms from the DAC – however, I want to be able to generate other types of signals from the DAC, such as pulse waves and frequency modulated continuous waves. Due to the sequential nature of Python, I am not sure how to have a transmitter signal that changes, while the receiver is receiving. Perhaps I have to use multithreading/multiprocessing, but I’m not sure if that is overcomplicating it, or maybe it is simpler to design from the FPGA architecture.
Thanks
Hi @ak123,
No problem, and I think I can answer your question and offer some advice.
Python does execute commands sequentially due to the Global Interpreter Lock (GIL). However, you can use the FPGA portion of the RFSoC to perform concurrent processing for the transmitter and receiver. Additionally, as I mentioned before, there isn’t any out-of-the-box infrastructure to help you generate arbitrary signals, so you will need to design your own FPGA architecture design, which can be a little tricky if you are new to this. Here are a few tools to get you started:
It sounds like you want a transmitter and receiver operating simultaneously, which is possible using the FPGA logic fabric. However, to help you progress, my advice is to focus on just one part of the system at the moment and try to list, using bullet points, precisely what you would like to achieve. Then, try sketching out a diagram based on your specification. From here, you can start designing the system components using the tools I have given above for FPGA implementation. It would be best if you have a good understanding of digital electronics to proceed here.
You can see some design examples that the StrathSDR team have implemented below:
And, of course, you have the base overlay for the RFSoC4x2, which will show you how to interact with the RF Data Converters on this platform.
Hopefully, this is useful,
Thanks,
David.
Hi David,
Thanks, this was very helpful!
What would designing my own FPGA architecture constitute? With an FPGA design, I would be directly coding the PL, so I would no longer need an overlay from what I understand. Or would I still need to interface PYNQ with the HDL?
Are there any sample HDL (VHDL or Verilog) tutorials for the RFSoC4x2 that you can point me to?
Also, can you please point me in the right direction regarding loading in a new overlay (which files are necessary – tcl, bit, hwh – and where do I upload them?
I am new to the RFSoC4x2/PYNQ framework so I am still trying to understand how everything works.
Thanks for all the help.
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Modern Electronic Warfare (EW) systems must handle an avalanche of RF signals across wide frequency ranges. Whether it’s detecting agile radar pulses or intercepting bursty communications, the ability to capture and process high-bandwidth data in real time is critical. One of the toughest challenges in EW today is capturing high-frequency, wideband signals with fast analog-to-digital converters (ADCs) and processing them quickly. Missing a fleeting frequency hop or a short radar pulse could mean missing a threat.
Recent advancements – like integrating fast RF-sampling converters and FPGAs into a single Radio Frequency System-on-Chip (RFSoC) – enable EW receivers to directly sample wide swaths of spectrum. However, these RFSoC devices can produce data streams on the order of hundreds of gigabits per second, pushing the limits of traditional recording and storage methods. This is where high-speed Ethernet-based recorders come in: they provide a way to stream and store huge volumes of digitized RF data in real time, without packet loss, for immediate or post-mission analysis.
In summary, fast data capture and processing are no longer luxuries in modern EW – they’re necessities to keep up with advanced threats.
To illustrate the need for a high-speed recorder, consider a radar threat analysis application. In this scenario, an EW system is tasked with intercepting and analyzing enemy radar signals (for example, an airborne early warning radar or a fire-control radar on an adversary’s platform). Modern radars often employ wideband, agile waveforms – a pulse might be frequency-hopping across hundreds of MHz or using a wide chirp bandwidth.
The EW receiver must capture these pulses across a broad spectrum in real time to identify the radar’s characteristics. This demands a wide instantaneous bandwidth and high dynamic range from the receiver. Generating and capturing pulsed RF signals in real time across a very wide frequency range is inherently difficult and requires high-bandwidth equipment.
A 100 GbE recorder in this application allows continuous recording of the incoming wideband signal stream. Instead of just observing snapshots, engineers can record minutes or hours of raw IQ data covering the full radar bandwidth. This is invaluable for post-mission analysis: one can extract pulse timing, modulation patterns, frequency hops, and other fingerprints of the threat radar.
In short, wideband signal capture with an Ethernet recorder ensures that no critical signal is missed, enabling thorough radar threat analysis and robust Electronic Support Measures (ESM).
The RFSoC board is the front-end that directly interfaces with the signals from the RF Frontend and antennas. For example, the RFSoC 4×2 board (built around the Zynq UltraScale+ RFSoC) integrates four 5 GS/s ADCs (up to 2.5 GHz bandwidth) and two 9.85 GS/s DACs on the same chip, alongside a large FPGA fabric and multi-core ARM processor.
This monolithic design eliminates the need for separate ADC cards and FPGA boards – the RFSoC handles both digitization and initial processing.
Notably, the RFSoC 4×2 includes a QSFP28 high-speed networking port, which can be configured as 4×25 Gbps, 2×50 Gbps, or 1×100 Gbps Ethernet. In our system, this port is used to stream digitized data off the board.
The FPGA on the RFSoC is programmed to packetize the ADC samples (for example, into Raw IQ UDP packets or a standard like VITA-49) and send them out over this 100 GbE link in real time. The RFSoC can also perform some real-time DSP – e.g. digital down-conversion, filtering, or channelization – to reduce data volume or isolate signals of interest before streaming, but it will still output a very high data rate.
The second major component is the Ethernet recorder, essentially a high-speed streaming storage system. This is typically a rackmount server or specialized recorder appliance equipped with a 100 GbE network interface (often a QSFP28 port to match the RFSoC) and an array of fast storage drives.
The recorder connects to the RFSoC board via a 100 GbE fiber or copper cable (e.g. an MPO optical cable if using optical transceivers). It is designed to ingest the 100 Gbps data stream in real time and write it to disk at full line rate.
Modern recording systems can sustain about 12.5 GB/s write speeds (100 Gigabits per second) to disk, often using RAID0 sets of NVMe SSDs. For instance, Daqscribe MDR Carbon100 recorder uses six NVMe drives in parallel and an AMD CPU to achieve 100 Gbps recording with up to 75TB of storage. That capacity equates to several hours of multi-channel wideband recording in a small form-factor. If higher bandwidths are required, the DDR Hyperion400 can support up to 400 Gbps with up to 720TB storage.
In our architecture, the recorder is configured to listen for the RFSoC’s UDP streams on the 100GbE interface. It can capture multiple channels simultaneously – for example, up to four independent ADC streams over a single 100GbE link – and saves each stream to its own file in real time. The data recorded is typically the “payload” of the Ethernet packets (the IQ samples), often stored in a standard format that can be later parsed for analysis. Meanwhile, the recorder’s software, nStudio, provides feedback on the data flow (packet counters, throughput, etc.) to ensure no data is lost.
The overall data flow pipeline thus looks like:
If we were to record IQ instead of Raw RF, we must double our bandwidth since we need two channels I and Q.
However, the 100GbE interface on the RFSoC4x2 can only handle 12.5 GB/s, meaning we cannot stream all four channels at full rate without dropping data. To fit within this limit, we have a few options:
By implementing decimation or selective streaming, the system stays within 100GbE limits while still capturing high-quality wideband RF data for analysis.
*The Xilinx RFDC (RF Data Converter) ADC block streams out data at 16bit, however, only the 14 MSB bits are relevant.
Begin by connecting the RFSoC board’s QSFP28 100 GbE port to the recorder’s 100 GbE network port. Depending on the hardware, this may involve inserting a 100G optical transceiver module into the QSFP28 cage on each end and running an MPO fiber cable between them. (Some setups use direct-attach copper cables if the distances are short.) Ensure both the RFSoC board and the recorder are powered on and properly configured for 100G link operation (the link status LEDs on the QSFP28 ports should indicate an active link). The RFSoC 4×2’s networking must be configured to match the recorder’s settings – typically, you’ll assign an IP address to the RFSoC’s 100GbE interface or use a raw Ethernet mode as required by the recorder. No special external trigger connections are needed; all data will flow through the 100G link.
On the RFSoC side, load the FPGA design that implements the high-speed data source. For an actual EW capture, this design would take samples from the RFSoC’s ADCs, perhaps apply some signal processing, and then format the data into Ethernet packets. In a demo or lab test, you might use a simple pattern generator or loopback: for instance, have the RFSoC transmit a known test waveform or even a PRBS (pseudo-random bit sequence) over 100GbE. The key is that the RFSoC is now streaming data at a very high rate. Many RFSoC reference designs provide example 100GbE UDP streaming logic. Make sure to set the destination IP/port to what the recorder expects (or use a predetermined protocol if the recorder is protocol-agnostic). At this stage, the RFSoC’s processor (ARM cores) can be used to control the streaming—starting and stopping the flow, adjusting parameters, etc., via software.
On the recorder system, launch the recording software and prepare it to capture the incoming stream. Typically, you would define a recording session specifying which interface to capture from (the 100GbE port) and any filtering or channel setup (for example, capture all UDP packets on a certain port, or capture multiple streams separately). In our case, since we expect up to four independent streams from the RFSoC, the recorder can be set to listen for up to 4 UDP ports and save each to a separate file simultaneously. Ensure the storage array on the recorder has enough space and the system is optimized for the high write rate (these recorders usually have large RAM buffers to handle bursts). Once everything is ready, arm the recorder (essentially “press record”). The system should now be waiting and ready to write incoming data to disk.
With both sides set up, start the data flow. This might be as simple as initiating the transmit function on the RFSoC application or toggling a GPIO that tells the FPGA to begin sending ADC data. Immediately, you should see the recorder registering the incoming stream – e.g. the software will show a rising throughput meter, ideally near 100 Gbps utilization. In real EW use, this is the moment the RFSoC is digitizing live RF signals (from an antenna or a signal generator) and streaming them out. Let the capture run for a short period for the demo (say, capture a few seconds of data which at 12.5 GB/s will already be tens of gigabytes). Then stop the RFSoC stream and stop the recorder. The recorder should now have saved data files, each containing the raw digitized samples from one channel (or whatever format was transmitted).
Now for the payoff – evaluating the captured data. High-speed recorders typically come with built-in tools to review the data. For example, the Mercury SystemFlow software includes a Signal Viewer utility for basic analysis. An engineer can open the recorded file and immediately view the waveform or spectrum to ensure the signal was captured correctly. If we transmitted a known test pattern, we can verify it bit-for-bit. In a real scenario (say we recorded live radar pulses), we could zoom in on the timeline to measure pulse widths and intervals, or perform an FFT to examine the spectrum. The captured files can also be loaded into standard analysis programs. Many recorders save in standard formats (like PCAP or binary IQ), so tools like MATLAB, Python scripts, or even Wireshark (for packet-level inspection) can be used to further analyze the data. The main point is that engineers now have a permanent recording of the RF signal which can be scrutinized in detail. They might discover, for instance, a faint low-power emitter in the background of the recordings or verify that a radar’s frequency hop pattern matches expectations. This ability to capture and then post-analyze wideband data gives EW engineers tremendous insight that real-time processing alone might miss.
Throughout this demonstration, the performance benefits of using a 100GbE link become clear. The RFSoC4x2 board is able to stream all four ADC channels to our ethernet recorder without dropping any packets.
The recorder, for its part, captures everything cleanly with no packet loss, something impossible on slower interfaces. In our next blog series, we’ll go into detail how to capture all four channels without decimation, using the DDR Hyperion400.
By evaluating the recorded data, engineers can confirm that their system meets its requirements (e.g., it can handle the intended bandwidth) and they gain confidence that in a real deployment, the system will not miss critical signals.
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